`ifndef MXU_INTF_SVH
`define MXU_INTF_SVH

interface mxu_cfg_if (
    input clk,
    input rst_n
);
    logic      vld;
    logic      rdy;
    logic      psum_en;
    logic      bias_en;
    lmb_addr_t lmb_addr;
    rmb_addr_t rmb_addr;
    pmb_addr_t pmb_addr;
    psb_addr_t psb_addr;
    idx_t      slice_m;
    idx_t      slice_n;
    idx_t      slice_k1;
    modport lmb_in(input vld, input lmb_addr, input slice_m, input slice_n, input slice_k1, output rdy);
    modport lmb_out(output vld, output lmb_addr, output slice_m, output slice_n, output slice_k1, input rdy);
    modport rmb_in(input vld, input rmb_addr, input slice_m, input slice_n, input slice_k1, output rdy);
    modport rmb_out(output vld, output rmb_addr, output slice_m, output slice_n, output slice_k1, input rdy);
    modport pmb_in(input vld, input pmb_addr, input slice_m, input slice_n, input slice_k1, output rdy);
    modport pmb_out(output vld, output pmb_addr, output slice_m, output slice_n, output slice_k1, input rdy);
    modport psb_in(input vld, input psb_addr, input slice_m, input slice_n, input slice_k1, output rdy);
    modport psb_out(output vld, output psb_addr, output slice_m, output slice_n, output slice_k1, input rdy);
    modport mat_ctrl_in(input vld, input slice_m, input slice_n, input slice_k1, output rdy);
    modport mat_ctrl_out(output vld, output slice_m, output slice_n, output slice_k1, input rdy);
endinterface

interface mxu_mat_ctrl_mat_array_if (
    input clk,
    input rst_n
);
    logic            vld;
    logic            rdy;
    logic      [1:0] mode;
    // 00: a*b; 01: a*b+c; 10: a*b+psum
    logic            lst_k;
    pack_16B_t       a     [`M0-1:0];
    pack_16B_t       b     [`N0-1:0];
    fp32_t           c     [`M0-1:0] [`N0-1:0];
    modport mat_ctrl_in(input vld, input mode, input lst_k, input a, input b, input c, output rdy);
    modport mat_ctrl_out(output vld, output mode, output lst_k, output a, output b, output c, input rdy);
endinterface

`endif
